1. Field of the Invention
The invention relates to data-processing systems, and more particularly, to an instruction mechanism for use in a high-performance, parallel-processing system.
2. Description of the Prior Art
Copending application Ser. No. 731,170 entitled "High Performance Computer System" of Stephen R. Colley, et al., filed on May 6, 1985, assigned to Ncube Corporation, and incorporated herein by reference, describes a parallel processor comprised of a plurality of processing nodes, each node including a processor and a memory. Each processor includes means for executing instructions, logic means connected to the memory for interfacing the processor with the memory and means for internode communication. The internode communication means connect the nodes to form a first array of order n having a hypercube topology. A second array of order n having nodes connected together in a hypercube topology is interconnected with the first array to form an order n+1 array. The order n+1 array is made up of the first and second arrays of order n, such that a parallel processor system may be structured with any number of processors that is a power of two. A set of I/O processors are connected to the nodes of the arrays by means of I/O channels. The means for internode communication comprises a serial data channel driven by a clock that is common to all of the nodes.
It is a primary object of the present invention to provide a new communication instruction mechanism for use in a data-processing architecture and apparatus utilizing parallel processing.